XNOR Gate Using NAND Gates

An XNOR logic Gate can be made using NAND logic gates. As we know, NAND is a universal logic gate, meaning it can be used to build other basic logic gates such as NOT, OR, AND, NOR, XOR, and XNOR. Implementing an XNOR gate using a NAND gate is useful when you need an XNOR logic circuit but only have NAND gates available; a XNOR logic gate is unavailable.

XNOR Logic Gate

An XNOR logic gate produces the output 1 (High) when its inputs are the same. The output becomes 0 (Low) when its inputs are different. For a 2-input XNOR gate, the output is 1 when both inputs are 0 or both inputs are 1. The XNOR logic gate truth table and its symbol are given below.

NAND Logic Gate

A NAND logic gate produces a LOW output (0) only when all its inputs are HIGH (1). In all other input combinations, the output is HIGH (1). Below are the truth table for the NAND logic gate and its symbols.

XNOR Gate Using NAND Gates

If we want to construct a 2-input XNOR logic gate using NAND gates, then 4-NAND gates are required to implement this process.

Let’s explain the above diagram

STEP 01: First NAND Gate

First NAND gate takes two inputs, A and B, and generates the output (A · B)’ as shown in the following diagram

This output is then connected to both the upper NAND gate and the lower NAND gate.

STEP 02: Upper NAND Gate

The upper NAND gate takes A as one input and the output of the first NAND gate, (A.B)’, as the other input. The following diagram explains the result of the upper NAND gate.

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STEP 03: Lower NAND Gate

The upper NAND gate takes B as one input and the output of the first NAND gate, (A.B)’, as the other input. The following diagram explains the result of the upper NAND gate.

Step 4: Second-to-Last NAND Gate

The second-to-last NAND gate takes the outputs of the upper and lower NAND gates as inputs.

Step 5: Second-to-Last NAND Gate

The final NAND gate takes the outputs of the second-to-last NAND gate and gives XNOR as a result.

XNOR Gate Using NAND Gates – Truth Table

A 2-input XNOR gate can be implemented using four NAND gates. The truth table below shows the output of the circuit for all possible combinations of inputs A and B.