OR Gate Using NAND Gate

An OR logic Gate can be made using NAND logic gates. As we know NAND is the universal logic gate, which means it can be used to make other basic logic gates such as OR, AND, NOT, XOR, XNOR etc. Implementation of OR gate using NAND gate can be used in the case when we need OR logic circuit but we have NAND gate instead of  OR gate.

OR logic gate and NAND logic gate, both are different in terms of output. so we have to implement NAND gate in such a way that its result are exact similar to OR logic gate.

OR Logic Gate

An OR logic gate produce the output 1 (High) when at least one input is 1 (High). Output  will becomes  0 (LOW) in only the case when all  inputs are 0 (LOW). OR logic gate truth table and its symbols is given below

NAND Logic Gate

An NAND logic gate produce the output 0 (LOW) in only the case when all  inputs are 1 (HIGH). For all other input combinations, the output is 1 (HIGH). NAND logic gate truth table and its symbols are given below

If we want to construct an OR gate which contains various number of inputs then Various Number of NAND gates are required to implement this process. let discuss various cases

2-inputs OR Logic Gate Using NAND Gate

If we want to construct an 2-inputs OR logic gate using NAND gates, then 3 NAND gates are required to implement this process. Let explain it in simple 2 steps

Step 01: Consider 2 NAND Logic Gates

First two NAND gates are used to take single input (i.e. A) at both ends of NAND, inputs are inverted because of NAND operation. If input is 0 it becomes 1 and vice versa. Both NAND gates produce A and B complements because of Idempotent Law law as shown in the following diagram

In the above diagram

• First NAND logic Gate takes A.A as input and produce A’.A’ which is equal to A’ (Idempotent Law)
• Second NAND logic Gate takes B.B as input and produce B’.B’ which is equal to B’ (Idempotent Law)

OR Logic Gate Using NAND Gate – Truth Table

Truth Table of Step 01 (2 inputs OR logic gates) is given below

Step 02: Take 3rd NAND Logic Gates

Third NAND logic gate takes the output of first two NAND gate as a input and produce the final OR output by using De Morgan’s Law  as shown in the following diagram

According to De Morgan’s Law, the third NAND gate produce the final OR gate output.

• Output : (A′ · B′)′ = A + B

OR Logic Gate Using NAND Gate – Truth Table

Truth Table of Step 02 (2 inputs OR logic gates) is given below

3-inputs OR Logic Gate Using NAND Gate

If we want to construct an 3-inputs OR logic gate using NAND gates, then 4 NAND gates are required to implement this process. Let explain it in simple 2 steps

Step 01: Consider 3-NAND Logic Gates

First 3-NAND gates are used to take single input (i.e. A) at both ends of NAND, inputs are inverted because of NAND operation. If input is 0 it becomes 1 and vice versa. All three NAND gates produce A, B and C complements because of Idempotent Law law as shown in the following diagram

In the above diagram

• First NAND logic Gate takes A.A as input and produce A’.A’ which is equal to A’ (Idempotent Law)
• Second NAND logic Gate takes B.B as input and produce B’.B’ which is equal to B’ (Idempotent Law)
• Third NAND logic Gate takes C.C as input and produce C’.C’ which is equal to C’ (Idempotent Law)

OR Logic Gate Using NAND Gate – Truth Table

Truth Table of Step 01 (3 inputs OR logic gates) is given below

Step 02: Take 4th NAND Logic Gates

Fourth NAND logic gate takes the output of all three NAND gate as a input and produce the final OR output by using De Morgan’s Law  as shown in the following diagram

According to De Morgan’s Law, the 4th NAND gate produce the final OR gate output.

• Output : (A′ · B′ . C’)′ = A + B + C

OR Logic Gate Using NAND Gate – Truth Table

Truth Table of Step 02 (3 inputs OR logic gates) is given below

4-inputs OR Logic Gate Using NAND Gate

If we want to construct an 4inputs OR logic gate using NAND gates, then 5-NAND gates are required to implement this process. Let explain it in simple 2 steps

Step 01: Consider 4-NAND Logic Gates

First 4-NAND gates are used to take single input (i.e. A) at both ends of NAND, inputs are inverted because of NAND operation. If input is 0 it becomes 1 and vice versa. All four NAND gates produce A, B, C and D complements. As shown in the following diagram

In the above diagram

• First NAND logic Gate takes A.A as input and produce A’.A’ which is equal to A’ (Idempotent Law)
• Second NAND logic Gate takes B.B as input and produce B’.B’ which is equal to B’ (Idempotent Law)
• Third NAND logic Gate takes C.C as input and produces C ‘. C ‘, which is equal to C’ (Idempotent Law)
• Fourth NAND logic Gate takes D.D as input and produce D’.D’ which is equal to D’ (Idempotent Law)

OR Logic Gate Using NAND Gate – Truth Table

Truth Table of Step 01 (4 inputs OR logic gates) is given below

Step 02: Takes 5th NAND Logic Gate

Fourth NAND logic gate takes the output of all four NAND gate as a input and produce the final OR output by using De Morgan’s Law  as shown in the following diagram

According to De Morgan’s Law, the 5th NAND gate produce the final OR gate output.

• Output : (A′ · B′ . C’. D ‘)′ = A + B + C + D

OR Logic Gate Using NAND Gate – Truth Table

Truth Table of Step 02 (4 inputs OR logic gates) is given below

In general an “n” input OR gate can be built using (n+1) NAND gates.