Common Bus System 

In this lecture, we will explain the common bus system with Single address instruction. Because the mechanism of a common bus system is best for single address instructions rather than two or three address instructions.

Purpose Of Common Bus System

Common Bus system is used to provides the path to transfer data from register to register or in-between the registers and memory. 

Common Bus System Diagram

In common bus system diagram there are 7 components (six registers and a single memory) are connected with a common bus. So, to represent these seven components of common bus system in binary, we require three select lines S0, S1, and S2.

Common Bus system in COA updated

Basic Components of Common Bus System

 Common Bus System uses a multiplexer to implement Common BUS.
• Memory and all Registers are connected through a common bus system.
• We consider 3 select lines (S0, S1, and S2) because we are using 7 inputs
to multiplexer as shown in the following diagram. With the help of 3 select lines,
8 inputs to multiplexer can be given.
• Select lines are 2n. It means how many total inputs can be added.
As 23=8x1(called 8 inputs and one output).

• If inputs are 4 or less than four, then we use two select lines i.e. S0 and S1 as

Tip: For example, When S2 S1 S0 = 010 then 2nd Input is activated. 

• 6 registers (AR, PC, DR, AC, IR and TR) and memory unit are connected to common bus. The DR (Data Register) is also connected with the ADDER and Logic Unit to perform operations on data through data Bus.

• INPTR (Input register) is not connected with the common bus. it receives data directly for Input device and sends it to Adder and Logic unit (part of ALU) for operations (+, -,*, /) and then pass it to Accumulator register. The adder and logic unit also contains a carry bit called (E) in case of addition.

OUTR (Output Register) does not send data to a common bus or any other register because it sends directly to the output device but it receives data from the common bus.

Important

  • Every register in the system is connected with Clock Signals.
  • Clock Signal controls LD, INR (increment), CLR (Clear register) commands by the control unit.
  • Memory read (R) and writes (W) operation also controlled by Control Unit.

Size of Registers In Common Bus System?

i. The Main memory is of 4096×16 = 2^12 x 16. To represent 4096 (2^12 ) memory we require 12 bits. So 12 bits are required to address 4096 Memory. X16 means 16 bits word, which will be access or transfer at a time when we move data from memory to registers.

ii. We require a common bus of 16 bits because word size is 16 bits and it has to pass through a common bus.

iii. AR and PC registers deal with the address of the memory so their sizes will be 12 bits. When the address of these registers arrives at a common bus its 4 most significant bits becomes zero.

iv. DR, AC, IR, and TR register deal with data of memory so there size will be 16 bits because word size is 16 bits.

v. Input register (INPR) and the output register (OUTR) send and receive data character by character, So, 8 bits required for INPR and OUTR Registers and communicate with 8 least significant bits in the common bus.

vi. Select lines bits value depends on how many components are connected with a common bus. Select lines follow the rule of 2^n where n is select lines bit value. 2 bits can represent 4 components (0-3). 3 bits require to represent 8(0-7) and so on.

How Common Bus System Works?

Step I: Any register can send its data to a common bus by activating its selected lines (S2, S1, S0).

Step II: If any register wants to receive data then its LD command will activate by setting the LD command value to 1. And LD command of all others registers set to zero.

Note: Activation/Deactivation of LD, INR or CLR of any register is done through a circuit called control unit.

Step III: Main process starts with the program counter.

  • Program counter fetches the address of memory which has to execute. And then pass this address to common bus.
  • AR receive the address from common bus by activating its LD bits. Then AR sends the address to memory directly because AR is directly connected with common bus.
  • Memory read the address and sends Data of that address to DR through common Bus.

Note: Other name of DR (data register) are MBR or MDR.

Step IV: Memory fetched data will be in DATA Register and then pass to Accumulator register by Data BUS because DR is directly connected with AC by Data Bus. Copy of this data is transfer to IR because when data pass to the accumulator register then Data Register will flush-out. So that the next incoming data in the next cycle can store. If the Accumulator register wants to store, (received data form DR) temporary in somewhere then it passes it to Temporary register (TR). If we want to retrieve the data from TR then its data is first loaded in DR and then it passes to AC.

Common Bus System Example

Suppose one address instruction is

X= (A+B) * (C+D)

To execute the above single address instruction, the system executes the following seven micro-instructions

LOAD A              //  AC <– M[A]
ADD B               //  AC <– AC + M[B]
STORE T            // Store AC value in temporary register
LOAD C             //  AC <– M[C]
ADD D              //  AC <– AC + M[D]
MUL T               // multiply temporary register value with AC
STORE X          // Store value of X in memory

Explanation of micro-instructions

As the program loads, the Program counter gets the address of the first instruction. For example, the first instruction is LOAD A. LOAD A means load value A to Accumulator register. It steps will be.

1. The first micro-instruction is LOAD A

It means to load the value A to Accumulator register.

  • The program counter (PC) gets the address of this instruction. The program counter will activate by select lines (010). And it transfers the address of an instruction to the common bus through the address register.
  • Through the control unit, the LD command of Address Register (AR) is activated in this way AR get the address of PC through a common bus.
  • The address register (AR) is directly attached to Main Memory.
  • When the address of instruction arrives at the main memory then the READ command of main memory will activate and data of the provided address is transferred to the common bus through the data bus.
  • Now LD command of data Register will activate and DR gets data from the common bus through the data bus.
  • The instruction in the MDR is then copied to the CIR. Data coming from memory (READ) or going to memory (Write) is always in Memory Data Register MDR (DR or MBR). Fetch the instruction is complete here, and now PC in Incremented by ONE. It means now Program counter having the address of next memory location in the sequence
  • Now data will transfer from MDR to Control unit (ALU section) where it will decode. In the decode section, Operator/opcode (like ADD, LOAD) are separate from Operand (data like A).
  • Now Data will transfer to Accumulator register by passing through ALU (for any operation like +,-), through a data bus.
  • Here the completion of the first micro-instruction.

2. The second micro-instruction is ADD B

This instruction means that ADD the value of B with accumulator register value, in Accumulator Register.

  • Value of “A” is already in accumulator register, now “+ B” arrives through STEP 1-7. Keep in mind in first instruction execution there was no need for the ALU section but in ADD B instruction ADDER and LOGIC-Unit perform addition first and then pass the value to AC Register.
  • Therefore, Now the value of AC will be of A+B.

3. The third micro-instruction is Store T.

It means that store the result of Accumulator in Temporary register (T). For this AC will activate through its select lines and passes data to the common bus.

LD command of TR will activate through the control bus of the control unit. And it gets data of AC Register from a common bus.

4. The fourth and fifth micro-instructions are LOAD C and ADD D.

These instructions will execute like LOAD A and ADD B. Till Here, the Accumulator register (AC) has the value of C+D.

5. Sixth micro-instruction is MUL T

It means that multiply the value of Temporary Register (T) with Accumulator Register. For this purpose, temporary register data is activated through select lines and pass to the common bus. LD command of DATA Register is activated by the control unit to get data and DR gets data from the common bus and then passes it to Accumulator Register. So now in AC is (A+B)*(C+D).

6. Seventh micro-instruction is STORE X

Now the value of AC can store in memory. So, seventh micro-instruction is STORE X.  It means to store the value of Accumulator Register (which is in X variable) into the main memory at the given address. for this AC will activate by its select lines and data of AC through Data bus is pass to common Bus and then go to MDR. Now memory Write command will activate through the control unit and memory gets data MDR and store value in X variable.

Note: If the user wants to display the results on Monitor then

Micro-instruction (Display X) can use which means that loads the value of X from memory in the Data Register and then pass it to the Display device (output device).

Advantage Of Common Bus System

If we use wires to define the path of each register to everyone with other registers and memory (like in Mesh topology), then It will be too complex and costly and difficult to implement.
So, the common bus system is an efficient way to transfer data from one register to other registers and registers to main memory.

Important Points in the common bus system

i. Question is that how the data move from the input device to an output device. The answer is that when we pass data from the input device (keyboard, mouse) then it will go directly to INPR (input register), input register pass it to ADDER and LOGIC unit, and then move to AC. AC passes it to a common bus and from the common bus, OUTR receives data and this data then pass to the output device to display.

ii. If we use only Address register (not use program counter register) then the Address register doesn’t know what to execute next. And don’t know where the next instruction located. It forgets the Memory location after executing the first instruction. PC keeps the address of the next instruction in the sequence of addresses.

iii. Memory fetched data will be in the DATA Register and then pass to the Accumulator register. When data passed to the accumulator register then Data Registered is cleared. So that next incoming data may store. If the Accumulator register wants to store this data somewhere temporarily then it passes it to the Temporary register (TR). If we want to retrieve the data from TR then its data is first loaded in DR and then pass to AC.

iv. If we use only Address register (not use program counter register) then the Address register doesn’t know what to execute next. And don’t know where the next instruction located. It forgets the Memory location after executing the first instruction then PC keeps the address of the next instruction in the sequence of addresses.

v. The DR is a two-way register because data going to memory or coming from memory always be in the DR register.

 

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