Page Table Entries
Page table contains many entries, and each page table entry contains a frame number and optional status like present/Absent bit, Protection, Reference, Caching, and Dirty bit.
Following is very simple but descriptive diagram of page table entries
let explain the each component of page table entries
1. Frame Number:
It gives the frame number of the main memory for the required page.
2. Present/absent bit:
The present or absent bit tells about the presence or absence of a particular page you are looking for in the main memory. If the required page is found, it is a case of Page Hit, denoted by 1. When a required page is not found, it results in a page fault, which is indicated by 0. Page fault is controlled by OS, using the virtual memory concept.
3. Protection bit:
The protection bit tells about the protection that you want to apply on that page. There are three permissions available on any page: read, write, and execute.
4. Referenced Bit
The referenced bit tells whether this page has been accessed in the last clock cycle or not. If it is accessed earlier, then the reference bit is set to 1. If this page referred first time then reference bit set to 0. It is used in memory access algorithms like LRU, etc.
5. Caching Enabled/Disabled
The cache is a memory that is faster and closer to the CPU. The least Recently used information is stored in the Cache. The cache can be enabled or disabled for pages.
Sometimes, we need the fresh data (Dynamic). If we use an account and our balance dynamically changes with time, then in such cases, keep the cache disabled.
Sometimes, we need the Static data as a video, which we use again and again. Then, for this type of task, a cache can be enabled.
6. Modified bit:
It is also called a dirty bit. It tells whether the page has been modified or not. If the value of modified bit is 1 then it means the value of this page is updated in RAM by CPU with the permission of Process Write. If dirty value=1, then OS will update the value of this page on the hard disk. If dirty value=0, then it means no change is performed in RAM by the CPU.
Page Table Entries Size
Page table entries (PTEs) size depends on the architecture of the system (32-bit or 64-bit), and sometimes even on specific paging modes used within those architectures.
32-bit Page Table Entries (Bit 1 = LSB, Bit 32 = MSB)
Let’s explain 32 bit a page table of 32 bits, where the first bit represents the least significant bit and the last 20 bits represent he most significant bits.
| Bit # | Name | Meaning if 0 | Meaning if 1 |
|---|---|---|---|
| 1 | Present (P) | Page is not in physical memory | Page is present in physical memory |
| 2 | Read/Write (R/W) | Page is read-only | Page is writable |
| 3 | User/Supervisor (U/S) | Access only by kernel (supervisor) | Access allowed by user-level processes |
| 4 | Page-Level Write-Through | Use write-back caching | Use write-through caching |
| 5 | Page-Level Cache Disable | Caching enabled for this page | Caching disabled for this page |
| 6 | Accessed (A) | Page has not been accessed | Page has been accessed (read/write) |
| 7 | Dirty (D) | Page has not been written to | Page has been written to |
| 8 | Page Attribute Table | Use default PAT memory type | Use PAT-defined memory type |
| 9 | Global (G) | Page is not global (flushed on context switch) | Page is global (not flushed) |
| 10–12 | Available for OS use | Depends on OS | Depends on OS |
| 13–32 | Page Frame Number (PFN) | Encodes the physical page frame address (upper 20 bits of physical address) |
Notes:
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Bit 1 is the least significant bit (LSB), so counting is right to left.
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Bits 13–32 (20 bits) form the Page Frame Number, which tells which physical memory frame this page maps to.
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Accessed and Dirty bits (6, 7) are typically set by the hardware.
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The Available bits (10–12) are often used by the OS for custom purposes like tracking status, protection, or page age.
64-bit Page Table Entry (PTE) Format
- Each PTE = 8 bytes = 64 bits
- Format: Bit 1 is LSB (rightmost), Bit 64 is MSB (leftmost)
| Bit # | Name | Meaning if 0 | Meaning if 1 |
|---|---|---|---|
| 1 | Present (P) | Page is not present in physical memory | Page is present in physical memory |
| 2 | Read/Write (R/W) | Page is read-only | Page is writable |
| 3 | User/Supervisor (U/S) | Supervisor (kernel) access only | Accessible from user mode |
| 4 | Page-level Write-Through | Use write-back caching | Use write-through caching |
| 5 | Page-level Cache Disable | Caching enabled for this page | Caching disabled |
| 6 | Accessed (A) | Page has not been accessed | Page has been accessed (read or written) |
| 7 | Dirty (D) | Page has not been written | Page has been written to |
| 8 | Page Size (PS) | Entry points to a page table (4 KB page) | Entry maps a large page (e.g., 2 MB / 1 GB) |
| 9 | Global (G) | Not global (flushed on context switch) | Global page (not flushed on context switch) |
| 10–11 | Available to OS | OS-defined | OS-defined |
| 12 | Page Attribute Table | Use default memory type | Use PAT-defined memory type |
| 13–51 | Page Frame Number (PFN) | — | Upper 39 bits of the physical frame address |
| 52–58 | Reserved / OS-available | OS-defined or reserved | OS-defined or reserved |
| 59 | Protection Key (PK) | No key or default | Uses protection key feature (if enabled) |
| 60 | Execute Disable (XD) | Page can be executed (code) | Page cannot be executed |
| 61–64 | Reserved / Architecture | Reserved or extended flags | Reserved or extended flags |
Notes:
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Bits 13–51 (39 bits) store the Page Frame Number — the physical address of the mapped page/frame (shifted left by 12 bits).
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Bit 60 (XD – Execute Disable) prevents execution of code from that page (helps with security like DEP).
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Bits 52–58 are often used by the operating system for custom purposes.
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Bit 8 (Page Size) is meaningful only in higher-level page tables (e.g., PDPTE, PDE), not in PTEs pointing to 4 KB pages.
32-bit PTE Vs 64-bit PTE
| Feature | 32-bit PTE | 64-bit PTE |
|---|---|---|
| Entry Size | 4 bytes | 8 bytes |
| Address bits (PFN) | 20 bits | 39 bits |
| Virtual address support | 4 GB | 48 bits (typical), up to 256 TB |
| New features | No execute-disable | Execute Disable (XD), Protection Key |
let discuss some questions of page table entry
1. Number of pages in virtual memory
Q: A system has a 32-bit virtual address space and uses a 4 KB page size. How many pages are there in virtual memory?
Solution:
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Virtual address space = 232 bytes
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Page size = 212 bytes
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Number of pages =232/212 bytes pages
Answer: 1,048,576 pages
2. Page table size
Q: Each page table entry is 4 bytes. How big is the page table for the above system (1,048,576 pages)?
Solution:
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Entries = 1,048,576
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Size per PTE = 4 bytes
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Page table size = 1,048,576×4 = bytes = 4 MB
Answer: 4 MB
3. Number of entries in a 64-bit page table (1-level)
Q: In a 64-bit system using 4 KB pages and 8-byte PTEs, how many entries fit in a single-level page table of one page?
Solution:
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Page size = 4 KB = 4096 bytes
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PTE size = 8 bytes
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Entries per table = 4096 / 8 = 512
Answer: 512 entries